Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains, which are chains of flip-flops that are used to form serial shift registers for applying test patterns at inputs to combinational logic of the integrated circuit and for reading out the corresponding results. A given one of the flip-flops of the scan chain may be viewed as an example of what is more generally referred to herein as a “scan cell.”
In one exemplary arrangement, an integrated circuit with scan test circuitry may have a scan shift mode of operation and a functional mode of operation. A flag may be used to indicate whether the integrated circuit is in scan shift mode or functional mode. In the scan shift mode, the flip-flops of the scan chain are configured as a serial shift register. A test pattern is then shifted into the serial shift register formed by the flip-flops of the scan chain. Once the desired test pattern has been shifted in, the scan shift mode is disabled and the integrated circuit is placed in its functional mode. Internal combinational logic results occurring during this functional mode of operation are then captured by the chain of scan flip-flops. The integrated circuit is then once again placed in its scan shift mode of operation, in order to allow the captured combinational logic results to be shifted out of the serial shift register formed by the scan flip-flops, as a new test pattern is being scanned in. This process is repeated until all desired test patterns have been applied to the integrated circuit.
As integrated circuits have become increasingly complex, scan compression techniques have been developed which reduce the number of test patterns that need to be applied when testing a given integrated circuit, and therefore also reduce the required test time. Additional details regarding compressed scan testing are disclosed in U.S. Pat. No. 7,831,876, entitled “Testing a Circuit with Compressed Scan Subsets,” which is commonly assigned herewith and incorporated by reference herein.
Nonetheless, in both compressed and noncompressed scan testing, there remains a need for further improvements in scan testing performance. For example, conventional scan test circuitry is susceptible to scan delay defects that can interfere with the scan shift mode of operation. Timing paths between adjacent scan cells in the scan shift mode may comprise simple wire connections or could include more complex arrangements of logic circuitry such as multiple logic gates which become transparent in the scan shift mode. These timing paths must meet flip-flop setup and hold times and other timing requirements in order for the scan shift mode to work properly. However, even though the timing requirements may be met in a given integrated circuit design, there could be timing paths that are marginal in nature that barely meet the timing requirements.
When a design of the type described above is implemented in a physical integrated circuit, a small deviation from nominal manufacturing parameters can lead to delay defects in one or more of the marginal timing paths, causing the scan shift process to fail at the intended scan shift frequency. For example, the delay on the timing path between two adjacent scan cells may exceed the scan clock period, such that timing requirements for the path are violated, leading to a failure in the scan shift process.